IBIS Macromodel Task Group

Meeting date: 07 June 2022

Members (asterisk for those attending):
Achronix Semiconductor:       Hansel Dsilva
Amazon:                       John Yan
ANSYS:                      * Curtis Clark
                            * Wei-hsing Huang
Cadence Design Systems:     * Ambrish Varma
                              Jared James
Google:                       Zhiping Yang
Intel:                        Michael Mirmak
                            * Kinger Cai
                              Alaeddin Aydiner
Keysight Technologies:      * Fangyi Rao
                              Majid Ahadi Dolatsara
                              Ming Yan
                              Radek Biernacki
                            * Rui Yang
Luminous Computing            David Banas
Marvell                       Steve Parker
Mathworks (SiSoft):         * Walter Katz
                              Mike LaBonte
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
Missouri S&T                  Chulsoon Hwang
SAE ITC                       Michael McNair
Siemens EDA (Mentor):       * Arpad Muranyi
Teraspeed Labs:             * Bob Ross
Zuken USA:                    Lance Wang

The meeting was led by Arpad Muranyi.  Curtis Clark took the minutes.

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Opens:

- Arpad noted that he had added a new item 7 to the agenda to track a list of
  upcoming topics that Zhiping had informed us were under development.

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Review of ARs:

- Arpad to send BIRD213.1 draft 28 to Randy to be posted.
  - Done.
  
- Randy to submit draft 28 to the IBIS Open Forum as BIRD213.1.
  -Done.

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Call for patent disclosure:

- None.

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Review of Meeting Minutes:

Arpad asked for any comments or corrections to the minutes of the May 31st
meeting.  Ambrish moved to approve the minutes.  Randy seconded the motion.
There were no objections.

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New Discussion:

Supporting PI simulation in IBIS:
Kinger presented an update on ongoing work to facilitate system level PI design
with chip level PI models in IBIS.  He referenced a presentation he had given
on Standard Power Integrity Model (SPIM) and Unified PI Target (UPIT) from the
2020 IBIS Summit at IEEE+SIPI.

SPIM:
 - The goal is to have IBIS provide a chip level model to facilitate platform PI
   design.
 - For each rail, it provides S-parameters from balls/pins to bump or on-die
   locations.
 - Provides weighted normalized AC source stimuli, since the chip vendor knows
   where the heavy and light loads will be.
 - Provides additional ports for observation points where Z(f) can be
   determined.
 - Provides BGA/pin awareness.  Specifies which pins are combined into which
   ports.
   
Walter asked how many ports you'd expected to have on the models for each of the
rail voltages.  Kinger said CPUs and GPUs are typically the biggest models.  He
said in a case where you might have hundreds of balls for a particular rail, the
model might be as large as 50 ports.  Typically, smaller parts may have 5 or 10
ports per rail.  He said they are typically balancing accuracy requirements but
trying to keep port counts well below 100.

Kinger said the normalize AC source has two characteristics.  The sources sum to
1, and they are distributed according to the load (e.g. .5 source at one port,
.3 at another, .2 at the third port with the lowest expected load).  He said the
AC modeling approach is fairly mature, and they're now adding DC as well.  They
are looking to add transient support to the approach later.  He said right now
to support transient you typically have to give too many details to customers.

For DC analysis, the same weighting information can be used to provide customers
with more information about the current distribution instead of assuming one
overall current value is split uniformly over the bumps.  This gives the most
accurate current distribution through the PDN of the package and the most
accurate distribution at the BGA.  This allows more accurate IR drop
calculations and DC analysis at the board level.

CVRM (Compact VR Model):
Kinger noted that an IEEE paper had been published on this topic.  He said that
after a VR has been well designed, and we know the equivalent bandwidth, it's
straightforward to make a simple compact VR model.

The compact VR Model works well in frequency and time domain models.  Using
these models through IBIS would provide models that can likely interact well
with S-parameters in circuit simulators.  He said existing PI models are often
specific to tools that may not handle S-parameters well.

Fast PI with UPIT:
- traditionally you only have one impedance target for PI design.
- Scalable UPIT can provide AC impedance targets in multiple frequency zones
  - zone 1 - package and Si interaction domain
  - zone 2 - package and board interaction domain
  - zone 3 - VRM and bulk caps domain
  
Kinger said traditionally zone 1 (region above 10 to 20MHz) is already well
handled by the chip vendors in their package and PDN designs.  So, generally
platform designers only have to worry about the region from l0kHz up to about
10 to 20MHz.  This approach gives platform designers the flexibility to place
caps and VRMs at their discretion, as long as they meet the impedance targets.

Kinger said the Fast PI Design Target is more of a transfer impedance
definition.  You provide the stimulus at N ports and monitor the impedance at
the observation port.

Kinger provided a brief organizational review of the SPIM models Intel has been
delivering to customers since 2017 (slide 9).

slide 10: proposed IBIS syntax
Kinger reviewed a proposed syntax they are working on for an .spi file in IBIS.
He said it was inspired by the .pkg files, and he noted that new
[Define Chip SPI Model] and [End Chip SPI Model] keywords could encapsulate
information that could be included in the .ibs file itself or a .spi file.

A separate [SPI Model] section would be provided for each power rail.
 - Bump level connection ports, sensing port, BGA connection ports
 - Ports are associated with groups of balls or bumps
   - port information could be provided in the .spi file or via a separate
     .port file
 - .sNp provided
 
Kinger reviewed a concrete example of the syntax.  He said that Chi-te Chen is
working on a cookbook describing best practices in creating these models.

Walter noted that bump/ball/pin to port mappings were similar in concept to
bus_labels.  Arpad and Walter noted that IBIS 7.0 had introduced interconnect
modeling syntax that can handle signal I/O and power distribution between balls
of the package and bumps on the chip, and between the bumps and I/O buffers.
They asked Kinger to review the interconnect modeling section to see if those
concepts could be adopted here to avoid duplication.  Kinger said he would
review the interconnect modeling syntax.

- Randy: Motion to adjourn.
- Bob: Second.
- Arpad: Thank you all for joining.
    
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Next meeting: 14 June 2022 12:00pm PT
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IBIS Interconnect SPICE Wish List:

1) Simulator directives
